Grain boundary potential barrier inhomogeneities in low-pressure chemical vapor deposited polycrystalline silicon thin-film transistors

Author

Dimitriadis, C.A.

Author_Institution

Dept. of Phys., Thessaloniki Univ., Greece

Volume

44

Issue

9

fYear

1997

fDate

9/1/1997 12:00:00 AM

Firstpage

1563

Lastpage

1565

Abstract

Arrhenius plots of conductivity in low-pressure chemical vapor deposited (LPCVD) polycrystalline silicon thin-film transistors (TFTs) are curved when the films are deposited at pressures below 40 mtorr. These deviations from straight lines are explained by spatial potential fluctuations over the grain boundary plane described by a Gaussian type distribution. When grain boundary inhomogeneities are not taken into account, the determined trap states density and the threshold voltage of the transistor are underestimated

Keywords

Gaussian distribution; chemical vapour deposition; electron traps; elemental semiconductors; grain boundaries; silicon; thin film transistors; 0 to 40 mtorr; Arrhenius plots; Gaussian type distribution; Si; grain boundary plane; grain boundary potential barrier inhomogeneities; low-pressure chemical vapor deposition; polysilicon thin-film transistors; spatial potential fluctuations; threshold voltage; trap states density; Chemicals; Conductive films; Conductivity; Current measurement; Fluctuations; Grain boundaries; Semiconductor films; Silicon; Thin film transistors; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.622619

Filename

622619