DocumentCode
1548502
Title
Comments on “Leading-zero anticipatory logic for high-speed floating point addition” [with reply]
Author
Oklobdzija, V. ; Suzuki, Hajime ; Makino, Hiroaki ; Nakase, Yasunobu ; Mashiko, K. ; Sumi, Takuya
Author_Institution
Integration, Berkeley, CA
Volume
32
Issue
2
fYear
1997
fDate
2/1/1997 12:00:00 AM
Firstpage
292
Lastpage
292
Abstract
For original article see H. Suzuki, H. Morinaka, H. Makino, Y. Nakase, K. Mashiko and T. Sumi, ibid., vol.31, pp.1157-69 (Aug. 1996). I have read with a great interest the article by H. Suzuki et al. I am familiar with their work, and I found their approach interesting. The idea used to simplify the leading zero anticipator (LZA) I found innovative and an improvement over the one used in the IBM RS/6000. However, I found the LZ counter circuit shown in the paper similar to the LZ counter circuit that I have published previously in the period from 1992-94
Keywords
floating point arithmetic; LZ counter circuit; high-speed floating point addition; leading-zero anticipatory logic; Algorithm design and analysis; Application specific integrated circuits; Asia; Circuit synthesis; Counting circuits; Delay; Detectors; Logic; Signal design; Tree data structures;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.551927
Filename
551927
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