Self-timed multiplier based on canonical signed-digit recoding

A data-dependent self-timed multiplier structure in dynamic logic and DCVS logic based on canonical signed-digit (CSD) recoding is presented. This coding increases the number of null partial products up to 33%, compared with the 25% of the traditional modified Booth recoding. The carry-save structure is a data-dependent parallel array, which uses this characteristic to reduce the number of addition operations, and thus increase the speed of the multiplier by 20% compared with other classical implementations. Thus, the adders of a null partial product become pass cells postponing the addition operation to the next stage. The layouts of a 16×16-bit and a 32×32-bit signed CSD multiplier have been devised. These present a rectangular-shaped structure and regular layout suitable for implementation in VLSI. Simulation results highlight that these CSD multipliers have a similar throughput to other pipeline asynchronous multipliers, but with a significant reduction of latency. The delay computation time is less than for published synchronous multipliers. However, the cost in terms of area and power is high