DocumentCode
1548660
Title
56 Gbit/s analogue PLL for clock recovery
Author
Schwarz, V. ; Willén, B. ; Jäckel, H.
Author_Institution
Electron. Lab., Swiss Fed. Inst. of Technol. Zurich, Switzerland
Volume
37
Issue
22
fYear
2001
fDate
10/25/2001 12:00:00 AM
Firstpage
1336
Lastpage
1338
Abstract
A clock-recovery circuit is reported that employs a phase-locked loop (PLL) at 56.88 Gbit/s, and is demonstrated by locking to a 28.44 GHz sinusoidal signal while two additional circuits with adapted on-chip passive components are locked to 29 and 39 Gbit/s pseudorandom bit sequences. To the knowledge of the authors, this is the first demonstration of an integrated PLL integrated circuit for clock recovery at a data rate well above 40 Gbit/s
Keywords
III-V semiconductors; bipolar analogue integrated circuits; data communication equipment; digital communication; gallium arsenide; heterojunction bipolar transistors; high-speed integrated circuits; indium compounds; phase locked loops; synchronisation; 28.44 GHz; 29 to 56.88 Gbit/s; InP-InGaAs; InP/InGaAs HBT process; PLL integrated circuit; analogue PLL; clock-recovery circuit; heterojunction bipolar transistor process; integrated PLL; phase-locked loop; pseudorandom bit sequences; sinusoidal signal;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20010893
Filename
964280
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