• DocumentCode
    1548958
  • Title

    Understanding branches and designing branch predictors for high-performance microprocessors

  • Author

    Evers, Marius ; Yeh, Tse-Yu

  • Author_Institution
    Adv. Micro Devices Inc., Sunnyvale, CA, USA
  • Volume
    89
  • Issue
    11
  • fYear
    2001
  • fDate
    11/1/2001 12:00:00 AM
  • Firstpage
    1610
  • Lastpage
    1620
  • Abstract
    Branch prediction is important in high-performance processors and its importance continues to grow. In the drive for higher execution frequencies, pipelines are lengthened and memory latencies are increased. This increases the cost of branch mispredictions. In this paper we describe some behavior patterns of branches. We believe that understanding the behavior of branches is helpful when designing fetch mechanisms for high-performance microprocessors. We also examine several current branch predictors and discuss how they work. Finally, we look at some of the challenges that we are faced with when designing fetch mechanisms and predictors for future microprocessors and discuss some of the possible solutions
  • Keywords
    integrated circuit design; microprocessor chips; parallel architectures; pipeline processing; branch predictor; fetch mechanism; memory latency; microprocessor design; pipelined processor; Accuracy; Bandwidth; Costs; Delay; Engines; Frequency; Microprocessors; Out of order; Pipelines; Prefetching;
  • fLanguage
    English
  • Journal_Title
    Proceedings of the IEEE
  • Publisher
    ieee
  • ISSN
    0018-9219
  • Type

    jour

  • DOI
    10.1109/5.964441
  • Filename
    964441