DocumentCode :
1549473
Title :
Dynamic pipeline design of an adaptive binary arithmetic coder
Author :
Kuang, Shiann Rong ; Jou, Jer Min ; Der Chen, Ren ; Shiau, Yeu Horng
Author_Institution :
Dept. of Electron. Eng., Southern Taiwan Univ. of Technol., Tainan, Taiwan
Volume :
48
Issue :
9
fYear :
2001
fDate :
9/1/2001 12:00:00 AM
Firstpage :
813
Lastpage :
825
Abstract :
Arithmetic coding is an attractive technique for lossless data compression but it tends to be slow. In this paper, a dynamic pipelined very large scale integration architecture with high performance for on-line adaptive binary arithmetic coding is presented. To obtain a high throughput pipelined architecture, we first analyze the computation flow of the coding algorithm and modify the operations whose data and/or control dependencies cause the difficulties in pipelining. Then, a novel technique called dynamic pipelining is developed to pipeline the coding process with variant (or run-time determined) pipeline latencies (or data initialization intervals) efficiently. As for data path design, a systematic design methodology of high level synthesis and a lower-area but faster fixed-width multiplier are applied, which implement the architecture with a little additional hardware. The dynamic pipelined architecture has been designed and simulated in Verilog HDL, and its layout has also been implemented with the 0.8-μm SPDM CMOS process and the ITRI-CCL cell library. Its simulated compression speeds under working frequencies of 25 and 50 MHz are about 6 and 12.5 Mb/s, respectively. About two times the speedup with 30% hardware overhead relative to the original sequential realisation is achieved
Keywords :
CMOS logic circuits; VLSI; adaptive codes; arithmetic codes; cellular arrays; data compression; hardware description languages; high level synthesis; multiplying circuits; pipeline arithmetic; probability; 0.8 micron; 12.5 Mbit/s; 25 MHz; 50 MHz; 6 Mbit/s; ITRI-CCL cell library; SPDM CMOS process; Verilog HDL; adaptive binary arithmetic coder; compression speeds; computation flow; data initialization intervals; dynamic pipeline design; fixed-width multiplier; hardware overhead; high level synthesis; on-line adaptive binary arithmetic coding; pipeline latencies; systematic design methodology; throughput; very large scale integration architecture; Algorithm design and analysis; Arithmetic; Computer architecture; Data compression; Data flow computing; Hardware design languages; Pipeline processing; Runtime; Throughput; Very large scale integration;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Publisher :
ieee
ISSN :
1057-7130
Type :
jour
DOI :
10.1109/82.964994
Filename :
964994
Link To Document :
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