Title :
Fault-secure parity prediction Booth multipliers
Author :
Nicolaidis, Michael ; Duarte, Ricardo O.
Author_Institution :
Reliable Integrated Syst. Group, TIMA Lab., Grenoble, France
fDate :
6/21/1905 12:00:00 AM
Abstract :
Parity prediction arithmetic operators are compatible with data paths and memory systems checked by parity codes. The authors extend their theory for achieving fault-secure design of parity prediction multipliers and dividers to Booth multipliers using operand recoding
Keywords :
digital arithmetic; fault tolerant computing; multiplying circuits; Booth multipliers; arithmetic operators; fault-secure design; operand recoding; parity prediction; Circuit topology; Complexity theory; Decoding; Digital arithmetic; Equations; Hardware; Routing; System testing;
Journal_Title :
Design & Test of Computers, IEEE
