Vertical bipolar transistors fabricated in local silicon on insulator films prepared using confined lateral selective epitaxial growth (CLSEG)

A new technique called the confined lateral selective epitaxial growth (CLSEG) process has been used successfully to produce thin local silicon-on-insulator (SOI) films of high material quality. Two different vertical bipolar transistor structures are fabricated in local SOI to evaluate the material quality and to demonstrate the versatility of the CLSEG technique. The first bipolar structure emitter is formed by ion implantation silicon and demonstrates maximum DC current gains (β _max) of 400 with junction ideality factors of less than 1.08. A second bipolar structure is fabricated which simultaneously forms both the emitter and subcollector regions. The subcollector is formed on the underside of the local SOI film by exposing it during the emitter phosphorus diffusion and serves to reduce parasitic collector resistance (r´_C). These nonoptimized underdiffused devices have measured β_max=158 and lower r´_C. A PISCES simulation accurately predicts the measured r´_C value and indicates values at least as low as 74 Ω in an optimized layout