• DocumentCode
    1550418
  • Title

    Compiler support for scalable and efficient memory systems

  • Author

    Barua, Rajeev ; Lee, Walter ; Arnarasinghe, S. ; Agarwal, Anant

  • Author_Institution
    Electr. & Comput. Eng. Dept., Maryland Univ., College Park, MD, USA
  • Volume
    50
  • Issue
    11
  • fYear
    2001
  • fDate
    11/1/2001 12:00:00 AM
  • Firstpage
    1234
  • Lastpage
    1247
  • Abstract
    Technological trends require that future scalable microprocessors be decentralized. Applying these trends toward memory systems shows that the size of the cache accessible in a single cycle will decrease in a future generation of chips. Thus, a bank-exposed memory system comprised of small, decentralized cache banks must eventually replace that of a monolithic cache. This paper considers how to effectively use such a memory system for sequential programs. This paper presents Maps, the software technology central to bank-exposed architectures, which are architectures with bank-exposed memory systems. Maps solves the problem of bank disambiguation-that of determining at compile-time which bank a memory reference is accessing. Bank disambiguation is important because it enables the compile-time optimization for data locality, where data can be placed close to the computation that requires it. Two methods for bank disambiguation are presented: equivalence-class unification and modulo unrolling. Experimental results are presented using a compiler for the MIT Raw machine, a bank-exposed architecture that relies on the compiler to 1) manage its memory and 2) orchestrate its instruction level parallelism and communication. Results on Raw using sequential codes demonstrate that using bank disambiguation improves performance, by a factor of 3 to 5 over using ILP alone
  • Keywords
    cache storage; memory architecture; parallel memories; program compilers; reconfigurable architectures; MIT Raw machine; Maps software; bank disambiguation; bank-exposed memory system; cache size; compile-time optimization; compiler support; data locality; efficient memory systems; equivalence-class unification; instruction level communication; instruction level parallelism; memory management; modulo unrolling; scalable memory systems; scalable microprocessors; sequential programs; small decentralized cache banks; Computer architecture; Delay; Logic; Memory architecture; Memory management; Microprocessors; Parallel processing; Registers; Scalability; Wire;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.966497
  • Filename
    966497