Rigel: A 1,024-Core Single-Chip Accelerator Architecture

Author

Johnson, Daniel R. ; Johnson, Matthew R. ; Kelm, John H. ; Tuohy, William ; Lumetta, Steven S. ; Patel, Sanjay J.

Author_Institution

Electr. & Comput. Eng. Dept., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA

Volume

31

Issue

4

fYear

2011

Firstpage

30

Lastpage

41

Abstract

Rigel is a single-chip accelerator architecture with 1,024 independent processing cores targeted at a broad class of data- and task-parallel computation. This article discusses Rigel´s motivation, evaluates its performance scalability as well as power and area requirements, and explores memory systems in the context of 1,024-core single-chip accelerators. The authors also consider future opportunities and challenges for large-scale designs.

Keywords

microprocessor chips; multiprocessing systems; parallel architectures; storage management; 1024 core single chip accelerator architecture; RlGEL; independent processing core; large scale design; memory system; performance scalability; power requirement; task parallel computation; Accelerator architectures; Coherence; Computational modeling; Hardware; Memory management; Programming; Multiple data-stream architectures (multiprocessors); multicore; multiple data processors; multiple instruction; parallel architectures; parallel processors; single-chip multiprocessors;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/MM.2011.40

Filename

5871571