• DocumentCode
    1550689
  • Title

    Concatenation of Functional Test Subsequences for Improved Fault Coverage and Reduced Test Length

  • Author

    Pomeranz, Irith

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
  • Volume
    61
  • Issue
    6
  • fYear
    2012
  • fDate
    6/1/2012 12:00:00 AM
  • Firstpage
    899
  • Lastpage
    904
  • Abstract
    Functional test sequences have several advantages over structural tests when they are applied at-speed. A large pool of functional test sequences may be available for a circuit due to the application of a simulation-based design verification process. This paper describes a versatile procedure that uses a pool of functional test sequences as a basis for forming a single compact functional test sequence that achieves the same or higher gate-level fault coverage than the given pool. The procedure extracts test subsequences from the test sequences in the pool and concatenates them to form a single test sequence. It also employs an enhanced static test compaction process aimed at improving the fault coverage in addition to reducing the test sequence length.
  • Keywords
    integrated circuit design; integrated circuit testing; sequential circuits; concatenation; fault coverage; functional test sequences; functional test subsequences; reduced test length; simulation-based design verification; single test sequence; Circuit faults; Compaction; Delay; Fault detection; Integrated circuit modeling; Logic gates; Manufacturing; Functional test sequences; stuck-at faults; synchronous sequential circuits; transition faults.;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2011.107
  • Filename
    5871591