Effect of dopant redistribution, segregation, and carrier trapping in As-implanted MOS gates

Author

Batra, Shubneesh ; Park, Keunhyung ; Lin, Jengping ; Yoganathan, Sittampalam ; Lee, Jack C. ; Banerjee, Sanjay Kumar ; Sun, Shih Wei ; Lux, Gayle

Author_Institution

Microelectron. Res. Center, Texas Univ., Austin, TX, USA

Volume

37

Issue

11

fYear

1990

fDate

11/1/1990 12:00:00 AM

Firstpage

2322

Lastpage

2330

Abstract

Anomalous capacitance-voltage behavior of arsenic-implanted polysilicon and amorphous Si gate MOS structures fabricated with and without a TiSi₂ layer is reported. The C-V characteristics and specifically the inversion and accumulation capacitances are gate-bias-dependent and are strongly affected by annealing temperature, silicidation, and polysilicon gate microstructure (i.e. polysilicon versus amorphous gate). The results can be explained by insufficient As redistribution, coupled with carrier trapping, and As segregation at polysilicon grain boundaries and in TiSi₂. All these effects lead to the formation of a depletion region in the polysilicon gate and thus to the anomalous C-V behavior

Keywords

arsenic; capacitance; insulated gate field effect transistors; ion implantation; titanium compounds; C-V characteristics; MOS gates; Si:As; TiSi₂ layer; accumulation capacitances; amorphous Si; annealing temperature; anomalous C-V behavior; capacitance-voltage behavior; carrier trapping; depletion region; dopant redistribution; dopant segregation; gate bias dependent capacitance; inversion capacitance; polycrystalline Si; polysilicon gate microstructure; polysilicon grain boundaries; silicidation; silicides; Amorphous materials; CMOS technology; Capacitance-voltage characteristics; Contracts; Grain boundaries; Implants; MOS devices; Silicides; Silicon; Temperature;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.62295

Filename

62295