Title :
The effects of source/drain resistance on deep submicrometer device performance
Author :
Jeng, Min-Chie ; Chung, James E. ; Ko, Ping-Keung ; Hu, Chenming
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fDate :
11/1/1990 12:00:00 AM
Abstract :
As MOSFET channel lengths approach the deep-submicrometer regime, performance degradation due to parasitic source/drain resistance (R sd) becomes an important factor to consider in device scaling. The effects of Rsd on the device performance of deep-submicrometer non-LDD (lightly doped drain) n-channel MOSFETs are examined. Reduction in the measured saturation drain current (Rsd=600 Ω-μm) relative to the ideal saturation current (Rsd=0.0 Ω-μm) is about 4% for Leff=0.7 μm and Tox =15.6 nm and 10% for Leff=0.3 μm and T ox=8.6 nm. Reduction of current in the linear regime and reduction of the simulated ring oscillator speed are both about three times higher. The effect of salicide technologies on device performance is discussed. Projections are made of the ultimate achievable performance
Keywords :
insulated gate field effect transistors; 0.3 micron; 0.7 micron; 15.6 nm; 8.6 nm; MOSFET channel lengths; deep submicrometer device performance; device scaling; drain resistance effects; effect of salicide technologies; measured saturation drain current; n-channel MOSFETs; parasitic source/drain resistance; performance degradation; ring oscillator speed; source resistance effects; ultimate achievable performance; Calibration; Computer simulation; Degradation; Electric resistance; Electrical capacitance tomography; Electrical resistance measurement; Fabrication; Guidelines; Immune system; MOSFET circuits;
Journal_Title :
Electron Devices, IEEE Transactions on
