The effects of source/drain resistance on deep submicrometer device performance

Author

Jeng, Min-Chie ; Chung, James E. ; Ko, Ping-Keung ; Hu, Chenming

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

37

Issue

11

fYear

1990

fDate

11/1/1990 12:00:00 AM

Firstpage

2408

Lastpage

2410

Abstract

As MOSFET channel lengths approach the deep-submicrometer regime, performance degradation due to parasitic source/drain resistance (R _sd) becomes an important factor to consider in device scaling. The effects of R_sd on the device performance of deep-submicrometer non-LDD (lightly doped drain) n-channel MOSFETs are examined. Reduction in the measured saturation drain current (R_sd=600 Ω-μm) relative to the ideal saturation current (R_sd=0.0 Ω-μm) is about 4% for L_eff=0.7 μm and T_ox=15.6 nm and 10% for L_eff=0.3 μm and T _ox=8.6 nm. Reduction of current in the linear regime and reduction of the simulated ring oscillator speed are both about three times higher. The effect of salicide technologies on device performance is discussed. Projections are made of the ultimate achievable performance

Keywords

insulated gate field effect transistors; 0.3 micron; 0.7 micron; 15.6 nm; 8.6 nm; MOSFET channel lengths; deep submicrometer device performance; device scaling; drain resistance effects; effect of salicide technologies; measured saturation drain current; n-channel MOSFETs; parasitic source/drain resistance; performance degradation; ring oscillator speed; source resistance effects; ultimate achievable performance; Calibration; Computer simulation; Degradation; Electric resistance; Electrical capacitance tomography; Electrical resistance measurement; Fabrication; Guidelines; Immune system; MOSFET circuits;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.62301

Filename

62301