Title :
Efficient test cost reduction procedure for parallel-serial scan circuits
Author_Institution :
Dept. de Electron. y Comput., Cantabria Univ., Santander, Spain
fDate :
10/11/2001 12:00:00 AM
Abstract :
An efficient test generation procedure aimed at reducing test application cost in parallel-serial scan (PASE-scan) circuits is presented. The procedure is based on the structure and configuration of this type of full-scan circuits. The results obtained with a set of ISCAS89 benchmark circuits are provided, showing the effectiveness of this technique as regards test clock reduction
Keywords :
integrated circuit testing; VLSI; full-scan design; parallel-serial scan circuit; test pattern generation;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20010868
