Title :
A flexible and expendable neuroimage processor architecture
Author :
Han, Gunhee ; Sánchez-Sinencio, Edgar
Author_Institution :
Yonsei Univ., Seoul, South Korea
fDate :
9/1/1999 12:00:00 AM
Abstract :
An analog versatile neuroimage processor (VNIP) architecture is proposed here. VNIP can process various types of neural network and image processing structures, without any hardware modification. The structure allows unlimited expansion of network size and the compensation of process variation. The proof-of-concept chip is implemented, using a combination of continuous-time multiplier and switched-capacitor techniques. The throughput is 12×106 synapses/s.mm2 and the energy consumption is 10-9 J/synapse. A test chip was fabricated, using a 1.2-μm double-poly CMOS process and tested, verifying the flexibility and expandability of the architecture
Keywords :
CMOS analogue integrated circuits; analogue processing circuits; continuous time systems; image processing equipment; neural chips; switched capacitor networks; 1.2 micron; VNIP; analog versatile neuroimage processor; continuous-time multiplier; double-poly CMOS process; energy consumption; expendable neuroimage processor architecture; network size; process variation; proof-of-concept chip; switched-capacitor techniques; unlimited expansion; Biology computing; Circuits; Computer architecture; Computer networks; Costs; Energy consumption; Image processing; Neural networks; Neurons; Testing;
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
