• DocumentCode
    1552068
  • Title

    SOI bipolar-MOS merged transistors for BiCMOS application

  • Author

    Zheng, Yue-Sheng ; Asano, T.

  • Author_Institution
    Center for Microelectron. Syst., Kyushu Inst. of Technol., Fukuoka, Japan
  • Volume
    35
  • Issue
    14
  • fYear
    1999
  • fDate
    7/8/1999 12:00:00 AM
  • Firstpage
    1203
  • Lastpage
    1204
  • Abstract
    A new MOSFET which has a built-in bipolar operation mechanism at the drain region has been fabricated using a bond-and-lap technique to form a silicon on insulator (SOI) structure. The results show that the merged transistors increase the transconductance by 15 times for a pMOS/npn transistor and by 60 times for an nMOS/pnp transistor as compared with conventional MOSFETs
  • Keywords
    BiCMOS logic circuits; integrated circuit measurement; integrated circuit technology; silicon-on-insulator; BiCMOS application; SOI; bipolar-MOS merged transistors; bond-and-lap technique; drain region; nMOS/pnp transistor; pMOS/npn transistor; transconductance;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19990812
  • Filename
    788970
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1552068