Title :
Fast evaluation of sequence pair in block placement by longest common subsequence computation
Author :
Tang, Xiaoping ; Tian, Ruiqi ; Wong, D.F.
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
fDate :
12/1/2001 12:00:00 AM
Abstract :
Murata et al. (1996) introduced an elegant representation of block placement called sequence pair. All block-placement algorithms that are based on sequence pairs use simulated annealing where the generation and evaluation of a large number of sequence pairs is required. Therefore, a fast algorithm is needed to evaluate each generated sequence pair, i.e., to translate the sequence pair to its corresponding block placement. This paper presents a new approach to evaluate a sequence pair based on computing longest common subsequence in a pair of weighted sequences. We present a very simple and efficient O(n2) algorithm to solve the sequence pair evaluation problem. We also show that using a more sophisticated data structure, the algorithm can be implemented to run in O (n log log n) time. Both implementations of our algorithm are significantly faster than the previous O(n2) graph-based algorithm. For example, we achieve 60 × speedup over the previous algorithm when input size n = 128. As a result, we can examine a million sequence pairs within one minute for typical input size of placement problems. For all MCNC benchmark block-placement problems, we have obtained the best results ever reported in the literature (including those reported by algorithms based on O tree and B* tree) with significantly less runtime. For example, the best known result for ami49 (36.8 mm2) was obtained by a B*-tree-based algorithm using 4752 s and we obtained a better result (36.5 mm2) in 31 s
Keywords :
circuit layout CAD; integrated circuit layout; sequences; simulated annealing; block placement algorithm; integrated circuit floorplanning; longest common subsequence computation; sequence pair; simulated annealing; Computational modeling; Costs; Data structures; Integrated circuit interconnections; Integrated circuit technology; Runtime; Simulated annealing; Transistors; Tree graphs; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on