DocumentCode :
1552140
Title :
Identification of primitive faults in combinational and sequential circuits
Author :
Tekumalla, Ramesh C. ; Menon, Premachandran R.
Author_Institution :
Corporate Computer-Aided Design Div., Sun Microsystems, Burlington, MA, USA
Volume :
20
Issue :
12
fYear :
2001
fDate :
12/1/2001 12:00:00 AM
Firstpage :
1426
Lastpage :
1442
Abstract :
This paper presents a method of primitive fault identification and test generation for combinational and nonscan sequential circuits. It uses the concept of sensitizing cubes to obtain input vectors that statically sensitize primitive faults in combinational circuits. The same technique is used to identify combinationally primitive faults in the next-state and output logic of sequential circuits. Such faults are primitive if and only if the fault effects on paths to state variable flip-flops can be propagated to a primary output (PO). Test sequences, including initializing sequences from a reset state and sequences that propagate fault effects from flip-flops to POs, are generated for primitive faults, wherever possible. The proposed method has been implemented and used to derive tests for primitive faults in the ISCAS´89 and MCNC´91 benchmark circuits. It was able to find all primitive faults and also obtain robust tests for a large fraction of them when the circuits were treated as combinational. When the same circuits were treated as nonscan sequential circuits, all primitive faults could not be found because fault propagation had to be limited to a relatively small number of time frames
Keywords :
automatic test pattern generation; binary sequences; circuit analysis computing; combinational circuits; computational complexity; delays; fault diagnosis; identification; integrated circuit testing; integrated logic circuits; logic testing; sequential circuits; timing; ATPG; combinational circuits; delay faults; initializing sequences; input vectors; nonscan sequential circuits; primary output; primitive fault identification; state variable flip-flops; test generation; test sequences; timing verification; Circuit faults; Circuit testing; Combinational circuits; Delay; Design automation; Fault diagnosis; Flip-flops; Robustness; Sequential analysis; Sequential circuits;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.969436
Filename :
969436
Link To Document :
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