Title :
Compact low voltage four quadrant CMOS current multiplier
Author :
Ravindran, A. ; Ramarao, K. ; Vidal, E. ; Ismail, M.
Author_Institution :
Dept. of Electr. Eng., Ohio State Univ., Columbus, OH, USA
fDate :
11/22/2001 12:00:00 AM
Abstract :
A new compact low voltage four quadrant current mode CMOS multiplier is presented. Post layout simulation in a CMOS 0.5 μm technology shows a linearity error lower than 0.9% for signal swings up to ±50 μA. The circuit operates at a supply of ±1.5 V, has a static power dissipation of 0.6 mW and a 1 dB bandwidth of 33 MHz
Keywords :
CMOS analogue integrated circuits; analogue multipliers; current-mode circuits; low-power electronics; 0.5 micron; 0.6 mW; 1.5 V; 33 MHz; bandwidth; compact low-voltage four-quadrant CMOS current multiplier; current-mode circuit; linearity error; post-layout simulation; signal swing; static power dissipation;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20010988
