• DocumentCode
    1552881
  • Title

    High-speed dual-modulus prescaler architecture for programmable digital frequency dividers

  • Author

    Tournier, É ; Sié, M. ; Graffeuil, J.

  • Author_Institution
    Lab. d´´Autom. et d´´Anal. des Syst., CNRS, Toulouse, France
  • Volume
    37
  • Issue
    24
  • fYear
    2001
  • fDate
    11/22/2001 12:00:00 AM
  • Firstpage
    1433
  • Lastpage
    1434
  • Abstract
    A new high-speed architecture for a dual-modulus prescaler N/N+1 divider is presented and compared to the widely used Johnson counter, in addition to some other approaches that have inherent limitations of speed when the ´+1´ of the N+1 divider is processed. This high-speed structure allows a speed similar to that of a simple divider-by-two from which it derives
  • Keywords
    delays; digital phase locked loops; frequency dividers; prescalers; PLLs; clock period; critical paths; dual-modulus prescaler architecture; high-speed architecture; programmable digital frequency dividers; propagation delay;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20010967
  • Filename
    970374
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1552881