Title :
CMOS switched current phase-locked loop
Author :
Leenaerts, D.M.W. ; Persoon, G.G. ; Putter, B.M.
Author_Institution :
Dept. of Electr. Eng., Tech. Univ. Eindhoven, Netherlands
fDate :
4/1/1997 12:00:00 AM
Abstract :
The authors present an integrated circuit realisation of a switched current phase-locked loop (PLL) in standard 2.4 μm CMOS technology. The centre frequency is tunable to 1 MHz at a clock frequency of 5.46 MHz. The PLL has a measured maximum phase error of 21 degrees. The chip consumes <2 mW from a 3.3 V power supply
Keywords :
CMOS digital integrated circuits; digital phase locked loops; switched current circuits; 2.4 micron; 3.3 V; 5.46 MHz; CMOS technology; centre frequency; clock frequency; integrated circuit realisation; maximum phase error; switched current phase-locked loop;
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings -
DOI :
10.1049/ip-cds:19970907
