High performance hardware accelerator for design-error simulation

Error simulation is used to validate designs by providing simulation results, as well as simulation coverage metrics, based on design-error modelling and detection. Hardware acceleration is a viable approach to achieve efficient error simulation for large systems. In this research, the first hardware accelerator for design-error simulation purposes has been developed. The hardware accelerator uses a reconfigurable mesh-type processing element array, with direct mapping strategy, which establishes a basis for good approximation to breadboarding. In addition, a new embedded parallel algorithm is introduced to perform high speed and cost-effective design-error simulation. Using a cost-performance ratio, the performance is compared to a software simulation. Results show that this first hardware accelerator for error simulation is much faster, in terms of computation time, than software simulation and more cost effective