An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis

In this paper, we present an effective and efficient framework to minimize clock latency range (CLR), which is a crucial objective measuring the process variability of the high-performance clock network. An enhanced deferred-merge embedding algorithm is proposed to handle the skew and slew constraints simultaneously. Besides, instead of using traditional buffering methods that consider only capacitance loading, we adopt slew-constrained buffering for more accurate results. To explore the variation effect with different combinations of buffers and wires in terms of CLR, we design an experiment to examine it and propose an effective buffer and wire sizing scheme. In addition, obstacle avoidance handling is included in our framework. Experimental results show that our framework achieves the best results in terms of CLR compared with any other team in the 2009 ACM ISPD clock network synthesis contest and four state-of-the-art works.