• DocumentCode
    1553952
  • Title

    Controller-based power management for control-flow intensive designs

  • Author

    Dey, Sujit ; Raghunathan, Anand ; Jha, Niraj K. ; Wakabayashi, Kazutoshi

  • Author_Institution
    Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
  • Volume
    18
  • Issue
    10
  • fYear
    1999
  • fDate
    10/1/1999 12:00:00 AM
  • Firstpage
    1496
  • Lastpage
    1508
  • Abstract
    This paper presents a low-overhead controller-based power management technique that redesigns control logic to reconfigure the existing data path components under idle conditions so as to minimize unnecessary activity. Controller-based power management exploits the fact that though the control signals in a register-transfer level implementation are fully specified, they can be respecified under certain states/conditions when the data path components that they control need not be active. We demonstrate that controller-based power management is often better-suited to control-flow intensive designs than comparable conventional power management techniques such as operand isolation. We present an algorithm to perform power management through controller redesign that consists of constructing an activity graph for each data path component, identifying conditions under which the component need not be active, and relabeling the activity graph resulting in redesign of the corresponding control expressions. We provide a comprehensive analysis of the potential side effects of controller-based power management on circuit delay, glitching activity at control and data path signals, and formation of false combinational cycles. Our algorithm avoids the above negative effects of controller-based power management to maximize power savings and minimize overheads. We present experimental results which demonstrate that (1) controller-based power management results in large power savings at minimal overheads for control-flow intensive designs, which pose several challenges to conventional power management techniques and (2) it is important to consider the various potential negative effects while performing controller-based power management in order to obtain maximal power savings
  • Keywords
    controllers; graph theory; logic CAD; power control; activity graph; algorithm; combinational cycle; control flow intensive design; controller redesign; data path component reconfiguration; delay; glitching activity; logic circuit; power management; register transfer level synthesis; CMOS logic circuits; Clocks; Delay effects; Energy consumption; Energy management; Logic design; National electric code; Reconfigurable logic; Registers; Signal analysis;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.790626
  • Filename
    790626