Reduction of leakage current at the gate edge of SDB SOI NMOS transistor

Author

Kang, Sung-Weon ; Lyu, Jong-Son ; Kang, Jin-Young ; Kang, Sang-won ; Lee, Jin-hyo

Author_Institution

Div. of Semicond., Electron. & Telecommun. Res. Inst., Taejon, South Korea

Volume

16

Issue

6

fYear

1995

fDate

6/1/1995 12:00:00 AM

Firstpage

236

Lastpage

238

Abstract

Leakage current through the parasitic channel formed at the sidewall of the SOI active region has been investigated by measuring the subthreshold I-V characteristics. Partially depleted (PD, /spl sim/2500 /spl Aring/) and fully depleted (FD, /spl sim/800 /spl Aring/) SOI NMOS transistors of enhancement mode have been fabricated using the silicon direct bonding (SDB) technology. Isolation processes for the SOI devices were LOCOS, LOCOS with channel stop ion implantation or fully recessed trench (FRT). The electron concentration of the parasitic channel is calculated by the PISCES IIb simulation. As a result, leakage current of the FD mode SOI device with FRT isolation at the front and back gate biases of 0 V was reduced to /spl sim/pA and no hump was seen on the drain current curve.

Keywords

MOSFET; 2500 angstrom; 800 angstrom; LOCOS; PISCES IIb simulation; SDB SOI NMOS transistor; SOI active region; channel stop ion implantation; drain current curve; electron concentration; enhancement mode transistors; fully depleted transistors; fully recessed trench; gate edge; isolation processes; leakage current reduction; parasitic channel; partially depleted transistors; silicon direct bonding technology; subthreshold I-V characteristics; Bonding; Current measurement; Etching; Ion implantation; Isolation technology; Leakage current; MOSFETs; Mirrors; Silicon; Threshold voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.790720

Filename

790720