DocumentCode :
1554326
Title :
A simple wafer-level measurement technique for predicting oxide reliability
Author :
Nariani, Subhash R. ; Gabriel, Calvin T.
Author_Institution :
VLSI Technol. Inc., San Jose, CA, USA
Volume :
16
Issue :
6
fYear :
1995
fDate :
6/1/1995 12:00:00 AM
Firstpage :
242
Lastpage :
244
Abstract :
A new wafer-level measurement technique, the differential gate antenna analysis, has been developed to detect weaknesses in sub-micrometer oxide. This simple technique involves the use of dual antenna structures with different gate oxide areas but the same antenna area ratio. The critical parameter is the difference in their failure levels. It is shown that such a differential measurement of antenna failures correlates with product failure during accelerated life testing. The differential antenna structures are thus proven useful for real-time wafer-level monitoring of oxide reliability.
Keywords :
CMOS integrated circuits; 0.6 mum; 13.5 nm; 5 V; ASIC; CMOS process; NMOS transistors; accelerated life testing; antenna area ratio; differential gate antenna analysis; dual antenna structures; failure level difference; gate oxide areas; high temperature operating life testing; oxide reliability monitoring; product failure; real-time wafer-level monitoring; submicrometer oxide weaknesses; wafer-level measurement technique; Antenna measurements; Condition monitoring; Costs; Gate leakage; Life estimation; Life testing; MOSFETs; Measurement techniques; Plasma measurements; Wafer scale integration;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/55.790722
Filename :
790722
Link To Document :
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