Title :
A fully integrated 40-Gb/s clock and data recovery IC with 1:4 DEMUX in SiGe technology
Author :
Reinhold, Mario ; Dorschky, Claus ; Rose, Eduard ; Pullela, Rajasekhar ; Mayer, Peter ; Kunz, Frank ; Baeyens, Yves ; Link, Thomas ; Mattia, John-Paul
Author_Institution :
Opt. Networking Group, Lucent Technol., Nurnberg, Germany
fDate :
12/1/2001 12:00:00 AM
Abstract :
In this paper, a fully integrated 40-Gb/s clock and data recovery (CDR) IC with additional 1:4 demultiplexer (DEMUX) functionality is presented. The IC is implemented in a state-of-the-art production SiGe process. Its phase-locked-loop-based architecture with bang-bang-type phase detector (PD) provides maximum robustness. To the authors´ best knowledge, it is the first 40-Gb/s CDR IC fabricated in a SiGe heterojunction bipolar technology (HBT). The measurement results demonstrate an input sensitivity of 42-mV single-ended data input swing at a bit-error rate (BER) of 10-10. As demonstrated in optical transmission experiments with the IC embedded in a 40-Gb/s link, the CDR/DEMUX shows complete functionality as a single-chip-receiver IC. A BER of 10-10 requires an optical signal-to-noise ratio of 23.3 dB
Keywords :
Ge-Si alloys; bipolar digital integrated circuits; demultiplexing equipment; digital phase locked loops; heterojunction bipolar transistors; optical receivers; phase detectors; semiconductor materials; synchronisation; 40 Gbit/s; SiGe; SiGe HBT technology; bang-bang phase detector; bit error rate; clock and data recovery IC; demultiplexer; input sensitivity; optical signal-to-noise ratio; optical transmission link; phase locked loop; single-chip receiver; Bit error rate; Clocks; Detectors; Germanium silicon alloys; Optical sensors; Phase detection; Photonic integrated circuits; Production; Robustness; Silicon germanium;
Journal_Title :
Solid-State Circuits, IEEE Journal of
