• DocumentCode
    1554761
  • Title

    Observable time windows: verifying high-level synthesis results

  • Author

    Bergamaschi, Reinaldo A. ; Raje, Salil

  • Author_Institution
    IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
  • Volume
    14
  • Issue
    2
  • fYear
    1997
  • Firstpage
    40
  • Lastpage
    50
  • Abstract
    Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors
  • Keywords
    formal verification; high level synthesis; behavioral specification; cycle-by-cycle behavior; high-level synthesis results; observable time windows; Analytical models; Application specific integrated circuits; Circuit simulation; Computational modeling; Design methodology; Hardware design languages; High level synthesis; Processor scheduling; Scheduling algorithm; Testing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.587740
  • Filename
    587740
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1554761