DocumentCode
1554765
Title
The K*BMD: A verification data structure
Author
Drechsler, Rolf ; Becker, Bernd ; Ruppertz, Stefan
Author_Institution
Freiburg Univ., Germany
Volume
14
Issue
2
fYear
1997
Firstpage
51
Lastpage
59
Abstract
Circuit designers can efficiently verify designs at the bit and word levels in one graph-based data structure. The authors present the representation technique, manipulation algorithms for K*BMDs, and experimental results other data structures
Keywords
Boolean functions; data structures; formal verification; integrated circuit design; logic CAD; logic testing; K*BMD; bit level; circuit design; graph-based data structure; manipulation algorithms; verification data structure; word level; Arithmetic; Benchmark testing; Boolean functions; Circuit testing; Circuits and systems; Data structures; Runtime; System testing; Very large scale integration;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/54.587742
Filename
587742
Link To Document