Title :
The K*BMD: A verification data structure
Author :
Drechsler, Rolf ; Becker, Bernd ; Ruppertz, Stefan
Author_Institution :
Freiburg Univ., Germany
Abstract :
Circuit designers can efficiently verify designs at the bit and word levels in one graph-based data structure. The authors present the representation technique, manipulation algorithms for K*BMDs, and experimental results other data structures
Keywords :
Boolean functions; data structures; formal verification; integrated circuit design; logic CAD; logic testing; K*BMD; bit level; circuit design; graph-based data structure; manipulation algorithms; verification data structure; word level; Arithmetic; Benchmark testing; Boolean functions; Circuit testing; Circuits and systems; Data structures; Runtime; System testing; Very large scale integration;
Journal_Title :
Design & Test of Computers, IEEE
