DocumentCode :
1555056
Title :
Fast IP packet delineator
Author :
Bourne, R.A. ; Phillips, C.I.
Author_Institution :
Dept. of Electron. Eng., Queen Mary & Westfield Coll., London, UK
Volume :
37
Issue :
25
fYear :
2001
fDate :
12/6/2001 12:00:00 AM
Firstpage :
1557
Lastpage :
1559
Abstract :
A fast-acting synchronisation mechanism for Internet Protocol (IPv4) packet delineation from an ingress bitstream is presented. It builds on delineation and scrambling mechanisms developed for asynchronous transfer mode (ATM) technology, but provides enhancements that cater for variable-sized packets. Implications of the scheme for IP version 6 are considered
Keywords :
packet switching; synchronisation; transport protocols; IP packet delineator; Internet Protocol; fast-acting synchronisation mechanism; ingress bitstream; scrambling mechanisms; variable-sized packets;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:20011023
Filename :
972214
Link To Document :
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