A scaled DCT architecture with the CORDIC algorithm

Author

Yu, Sungwook ; Swartzlander, Earl E., Jr.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

Volume

50

Issue

1

fYear

2002

fDate

1/1/2002 12:00:00 AM

Firstpage

160

Lastpage

167

Abstract

This paper presents an efficient approach for computing the N-point (N=2ⁿ) scaled discrete cosine transform (DCT) with the coordinate rotation digital computer (CORDIC) algorithm. The proposed algorithm is based on an indirect approach for computing the DCT so that the vector rotations are completely separated from the other operations and placed at the end of the DCT unit. As a result, unlike the other CORDIC-based DCT architectures, the proposed scaled DCT architecture does not require scale factor compensation. The number of CORDIC iterations is minimized through the optimal angle recoding method based on the three-value CORDIC algorithm. Although this three-value CORDIC algorithm results in different scale factors for different angles, this does not incur any extra hardware in the proposed scaled DCT architecture

Keywords

discrete cosine transforms; pipeline arithmetic; signal processing; CORDIC-based DCT architectures; VLSI implementation; coordinate rotation digital computer; discrete cosine transform; optimal angle recoding method; scale factor compensation; scaled DCT architecture; three-value CORDIC algorithm; vector rotations; Computer architecture; Discrete Fourier transforms; Discrete cosine transforms; Discrete transforms; Hardware; Helium; Image coding; Karhunen-Loeve transforms; Speech coding; Two dimensional displays;

fLanguage

English

Journal_Title

Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1053-587X

Type

jour

DOI

10.1109/78.972492

Filename

972492