FPGA Design for Statistics-Inspired Approximate Sum-of-Squared-Error Computation in Multimedia Applications

This brief introduces a low-cost hardware design for approximate squaring functions which preserve maximum information content of the signals in template-matching applications. Analysis of signal statistics for two example applications, i.e., motion estimation and disparity estimation, is presented. This information is then specifically incorporated in the hardware design process to develop approximate squarers which outperform existing designs in hardware resource savings and performance while processing real-world data. Specifically, the proposed architectures make distinction between low- and high-entropy portions of the input data to intelligently trade off bit precision with hardware complexity. Mathematical and experimental results show mean-relative-error figures to be as low as 1.2% and the performance to be as good as conventional full-precision processing scenarios. Implementation results for current-generation six-input look up table (LUT) and four-input LUT FPGAs have been discussed in relation to the proposed design flow.