DocumentCode :
1555559
Title :
Toward a systematic design methodology for large multigigahertz rapid single flux quantum circuits
Author :
Gaj, K. ; Herr, Q.P. ; Adler, V. ; Brock, D.K. ; Friedman, E.G. ; Feldman, M.J.
Author_Institution :
Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA
Volume :
9
Issue :
3
fYear :
1999
Firstpage :
4591
Lastpage :
4606
Abstract :
Rapid single flux quantum (RSFQ) digital circuits have reached the level of medium- to large-scale of integration. At this level, existing design methodologies, developed specifically for RSFQ circuits, have become computationally inefficient. Applying mature semiconductor methodologies to the design of RSFQ circuits, one encounters substantial difficulties originating from the differences between both technologies. In this paper, a new design methodology aimed at large-scale RSFQ circuits is proposed. This methodology is based on a semiconductor semicustom design approach. An established design methodology for small-stale RSFQ digital circuits, based on circuit (junction-level) simulation and device parameter optimization, is used for the design of basic RSFQ cells. A library composed of about 20 basic RSFQ cells has been developed based on this approach. A novel design methodology for large-scale circuits, presented in this paper, is based on logic (gate-level) simulation and timing optimization. This methodology has been implemented around the Cadence integrated design environment and used successfully at the University of Rochester for the design of two large-scale digital circuits.
Keywords :
circuit optimisation; logic CAD; logic simulation; superconducting logic circuits; timing; CAD process; Cadence integrated design environment; RSFQ cell library; RSFQ digital circuits; circuit simulation; device parameter optimization; gate-level simulation; junction-level simulation; large multigigahertz rapid single flux quantum circuits; large-scale RSFQ circuits; logic simulation; semiconductor semicustom design approach; systematic design methodology; timing optimization; Circuit simulation; Design methodology; Design optimization; Digital circuits; Large scale integration; Large-scale systems; Logic design; Logic devices; Logic gates; Software libraries;
fLanguage :
English
Journal_Title :
Applied Superconductivity, IEEE Transactions on
Publisher :
ieee
ISSN :
1051-8223
Type :
jour
DOI :
10.1109/77.791915
Filename :
791915
Link To Document :
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