Consistent floorplanning with hierarchical superconstraints

Sequence-pair-based floorplanning has revealed the limit of its usefulness in very large scale integration layout design, the key issue being that it is nonhierarchical and indifferent to the preceding step of partitioning. This paper restructures the sequence pair enhanced to a pair of logic expressions to accept the constraint induced by the previous step - the balanced bipartition. Since the bipartition is hierarchical in nature, the transferred constraint is called the hierarchical superconstraint. Since floorplanning based on this data structure automatically works cooperatively with the partitioning, it is called the consistent floorplanning, which has potential to store all the feasible floorplans under the constraint induced by any balanced binary search. As a typical example, we focus on clock-tree synthesis by H-tree. Experiments are given to show better achievements in length and wire density for module-based circuits and clock trees