• DocumentCode
    1555910
  • Title

    Dummy-feature placement for chemical-mechanical polishing uniformity in a shallow-trench isolation process

  • Author

    Tian, Ruiqi ; Tang, Xiaoping ; Wong, Martin D F

  • Author_Institution
    Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
  • Volume
    21
  • Issue
    1
  • fYear
    2002
  • fDate
    1/1/2002 12:00:00 AM
  • Firstpage
    63
  • Lastpage
    71
  • Abstract
    Manufacturability of a design that is processed with shallow-trench isolation (STI) depends on the uniformity of the chemical-mechanical polishing (CMP) step in STI. The CMP step in STI is a dual-material polish for which all previous studies on dummy-feature placement for single-material polish by Kahng et al. (1999), Tian et al. (2000), and Chen et al. (2000) are not applicable. Based on recent semiphysical models of polish-pad bending by Ouma et al (1998), local polish-pad compression by Grillaert (1999) and Smith (1999), and different polish rates for materials present in a dual-material polish by Grillaert (1999) and Tugbawa et al. (1999), this paper derives a time-dependent relation between post-CMP topography and layout pattern density for CMP in STI. Using the dependencies derived, the first formulation of dummy-feature placement for CMP in STI is given as a nonlinear-programming problem. An iterative approach is proposed to solve the dummy-feature placement problem. Computational experience on four layouts from Motorola is given
  • Keywords
    chemical mechanical polishing; design for manufacture; isolation technology; iterative methods; nonlinear programming; semiconductor process modelling; surface topography; chemical-mechanical polishing; design for manufacturability; dual-material polish; dummy feature placement; iterative method; layout pattern density; local polish-pad compression; nonlinear programming; planarity; polish rate; polish-pad bending; semiphysical model; shallow trench isolation; surface topography; Chemical processes; Etching; Iterative methods; Manufacturing; Process design; Production; Silicon; Strips; Surfaces; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.974138
  • Filename
    974138