Title :
Congestion estimation during top-down placement
Author :
Yang, Xiaojian ; Kastner, Ryan ; Sarrafzadeh, Majid
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
fDate :
1/1/2002 12:00:00 AM
Abstract :
Congestion is one of the fundamental issues in very large scale integration physical design. In this paper, we propose two congestion-estimation approaches for early placement stages. First, we theoretically analyze the peak-congestion value of the design and experimentally validate the estimation approach. Second, we estimate regional congestion at the early stages of top-down placement. This is done by combining the wire-length distribution model and interregion wire estimation. Both approaches are based on the well-known Rent´s rule, which is previously used for wirelength estimation. This is the first attempt to predict congestion using Rent´s rule. The estimation results are compared with the layout after placement and global routing. Experiments on large industry circuits show that the early congestion estimation based on Rent´s rule is a promising approach
Keywords :
VLSI; integrated circuit layout; integrated circuit modelling; network routing; Rent rule; VLSI design; congestion estimation; global routing; interregion wire estimation; top-down placement; wire-length distribution model; Annealing; Circuits; Computer science; Constraint optimization; Cost function; Logic design; Minimization; Routing; Very large scale integration; Wire;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on