DocumentCode :
1556089
Title :
Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converter
Author :
Mortezapour, Siamak ; Lee, Edward K F
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Volume :
34
Issue :
10
fYear :
1999
fDate :
10/1/1999 12:00:00 AM
Firstpage :
1350
Lastpage :
1359
Abstract :
A design technique that uses nonlinear digital-to-analog converter (DAC) for implementing low-power direct digital frequency synthesizer (DDFS) is proposed. The nonlinear DAC is used in place of the ROM look up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. Since the proposed design technique for DDFS does not require a ROM, significant saving in power dissipation results. The design procedure for implementing the nonlinear DAC is presented. To demonstrate the proposed technique, two quadrature DDFSs, one using nonlinear resistor string DACs and the other using nonlinear current-mode DACs, were implemented. For a 3.3-V supply, the resulting power dissipation for both DDFSs are 4 and 92 mW at a clock rate of 25 MHz and 230 MHz, respectively. For both DDFSs, the spurious free dynamic ranges are over 55 dB for low synthesized frequencies
Keywords :
current-mode circuits; digital-analogue conversion; direct digital synthesis; low-power electronics; 230 MHz; 25 MHz; 3.3 V; 4 mW; 92 mW; ROM-less design; clock rate; direct digital frequency synthesizer; low-power electronics; nonlinear current-mode DAC; nonlinear digital-to-analog converter; power dissipation; quadrature DDFS; spurious free dynamic ranges; Clocks; Communication switching; Digital-analog conversion; Feedback loop; Frequency synthesizers; Phase locked loops; Power dissipation; Read only memory; Table lookup; Wireless communication;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.792601
Filename :
792601
Link To Document :
بازگشت