Title :
A high lock-in speed digital phase-locked loop
Author :
Hao, Shi ; Puqiang, Yan
Author_Institution :
Dept. of Precision Instrum., Tsinghua Univ., Beijing, China
fDate :
3/1/1991 12:00:00 AM
Abstract :
A digital phase-locked loop (DPLL) consisting of a modified 9-gate phase detector, a frequency multiplier, and a loop filter is described. All the components are implemented in digital hardware. The Z-transform is employed to deduce the system function, and some simple properties of the DPLL are inferred by examining the mathematical model. The advantages of the proposed DPLL are: high lock-in speed, no steady-state frequency tracking error even for period ramp input signals; and ease of integration into a single chip. The use of the DPLL to realize the pitch synchronous analysis of voiced speech is reported
Keywords :
Z transforms; digital integrated circuits; phase-locked loops; speech analysis and processing; 9-gate phase detector; PLL; Z-transform; digital hardware; digital phase-locked loop; frequency multiplier; high lock-in speed; loop filter; period ramp input signals; pitch synchronous analysis; single chip; steady-state frequency tracking; system function; voiced speech; Design for manufacture; Filters; Frequency measurement; Hardware; Phase detection; Phase frequency detector; Phase locked loops; Sampling methods; Signal analysis; Steady-state;
Journal_Title :
Communications, IEEE Transactions on
