A cost-effective 8×8 2-D IDCT core processor with folded architecture

Author

Chen, Thou-Ho

Author_Institution

Dept. of Electron. Eng., Nan-Tai Inst. of Technol., Tainan, Taiwan

Volume

45

Issue

2

fYear

1999

fDate

5/1/1999 12:00:00 AM

Firstpage

333

Lastpage

339

Abstract

A dedicated cost-effective core processor of the 8×8 two-dimensional (2-D) inverse discrete transform (IDCT) architecture based on the direct realization approach is proposed. The folding scheme is developed to obtain a low gate-count and high throughput. The experimental result shows that the chip´s throughput is one pixel per clock cycle with a structure of 78 K transistors, which reveals that the low cost of VLSI implementation is more attractive than most of previously reported chips. With 0.6 μm CMOS, double metal technology, the chip is a standard-cell implementation and requires a core size of 4.4×2.8 mm², and is able to operate at a clock rate of more than 100 MHz

Keywords

CMOS digital integrated circuits; VLSI; code standards; decoding; digital arithmetic; digital signal processing chips; discrete cosine transforms; inverse problems; telecommunication standards; video coding; 0.6 micron; 100 MHz; 120 mW; 2D IDCT core processor; CMOS double metal technology; IDCT architecture; VLSI implementation; chip throughput; clock rate; core size; dedicated cost-effective core processor; direct realization approach; experimental result; folded architecture; folded matrix computation; high throughput; inverse discrete transform; low chip-area cost; low gate-count; standard-cell implementation; transistors; video decompression standards; CMOS technology; Clocks; Computer architecture; Discrete cosine transforms; HDTV; Image coding; Throughput; Transform coding; Very large scale integration; Video compression;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.793417

Filename

793417