Event-Driven GHz-Range Continuous-Time Digital Signal Processor With Activity-Dependent Power Dissipation

Presented is a clockless, continuous-time (CT) GHz processor that bypasses some of the limitations of conventional digital and analog implementations. Per-edge digital signal encoding is used for parallel processing of continuous-time samples with a temporal spacing as narrow as 15 ps, generated by a 3-b CT flash ADC. Parallel digital delay chains and programmable charge pumps realize the asynchronous filtering operation, each consuming negligible power while awaiting a new sample. A six-tap CT ADC and CT digital FIR processor system occupies 0.07 mm² and achieves dynamic range of over 20 dB in the 0.8-3.2-GHz signal range. The system´s rate of operations automatically adapts to the signal, thus causing its power dissipation to vary in the range of 1.1 to 10 mW according to input activity.