An efficient frame memory interface of MPEG-2 video encoder ASIC chip

Author

Kim, Kyeounsoo ; Koh, Jong-Seog ; Suh, Ki-Bum ; Chong, John-Wha

Author_Institution

Korea Telecom Access Network Lab., Seoul, South Korea

Volume

45

Issue

3

fYear

1999

fDate

8/1/1999 12:00:00 AM

Firstpage

507

Lastpage

514

Abstract

This paper presents an efficient frame memory interface of MPEG-2 video encoder which is accomplished in not only reducing interface buffer size through efficient memory map organization and access timing schedules but also avoiding unnecessary small size buffers and simplifying their control circuits. In this design, 0.5 μm CMOS TLM (triple layer metal) standard cells are used as design libraries, and VHDL simulator and logic synthesis tools are used for hardware design and verification, and the hardware emulator that is a C-language model of the proposed architecture is exploited for various test vector generation and functional verification. The improved frame memory interface module takes about 58% less hardware area than the previous design (Kim et al. 1997), and results in reducing the total hardware area of the video encoder ASIC chip up to 24.3%. We also reduced the random memory accesses to save the power consumption caused by the transition of the system-level I/O buses

Keywords

CMOS memory circuits; SRAM chips; application specific integrated circuits; buffer storage; digital signal processing chips; formal verification; integrated circuit layout; memory architecture; scheduling; video coding; 0.5 micron; C-language model; CMOS TLM standard cells; MPEG-2 video encoder ASIC chip; VHDL simulator; access timing schedules; control circuits; design libraries; efficient frame memory interface; efficient memory map organization; functional verification; hardware area; hardware design; hardware emulator; interface buffer size; logic synthesis tools; power consumption; random memory accesses; system-level I/O buses; test vector generation; triple layer metal; verification; video encoder ASIC chip; Application specific integrated circuits; CMOS logic circuits; Circuit simulation; Hardware; Libraries; Logic design; Logic testing; Scheduling; Size control; Timing;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.793534

Filename

793534