• DocumentCode
    1556997
  • Title

    Testability-Driven Statistical Path Selection

  • Author

    Chung, Jaeyong ; Xiong, Jinjun ; Zolotov, Vladimir ; Abraham, Jacob A.

  • Author_Institution
    Synopsys, Inc., Mountain View, CA, USA
  • Volume
    31
  • Issue
    8
  • fYear
    2012
  • Firstpage
    1275
  • Lastpage
    1287
  • Abstract
    In the face of large-scale process variations, statistical timing methodology has advanced significantly over the last few years, and statistical path selection takes advantage of it in at-speed testing. In deterministic path selection, the separation of path selection and test generation is known to require time consuming iteration between the two processes. This paper shows that in statistical path selection, this is not only the case, but also the quality of results can be severely degraded even after the iteration. To deal with this issue, we consider testability in the first place by integrating a satisfiability (SAT) solver, and this necessitates a new statistical path selection method. We integrate the SAT solver in a novel way that leverages the conflict analysis of modern SAT solvers, which provides more than 4X speedup without special optimizations of the SAT solver for this particular application. Our proposed method is based on a generalized path criticality metric whose properties allow efficient pruning. Our experimental results show that the proposed method achieves 47% better quality of results on average, and up to 361X speedup compared to statistical path selection followed by test generation.
  • Keywords
    automatic test pattern generation; computability; electronic engineering computing; SAT solver; at-speed testing; automatic test pattern generation; conflict analysis; deterministic path selection; large-scale process variation; satisfiability; statistical timing methodology; testability-driven statistical path selection; Automatic test pattern generation; Clocks; Delay; Phase change materials; Automatic test pattern generation; delay test; incremental satisfiability; statistical timing analysis;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2012.2190067
  • Filename
    6238392