Design and implementation of a DAB channel decoder

Author

Shieh, Ming-Der ; Wu, Chien-Ming ; Chou, Hsiao-Hsing ; Chen, Min-Hui ; Liu, Chia-Liang

Author_Institution

Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan

Volume

45

Issue

3

fYear

1999

fDate

8/1/1999 12:00:00 AM

Firstpage

553

Lastpage

562

Abstract

This paper describes the design of the de-interleaver and punctured Viterbi decoder for the Eureka-147 DAB system and their corresponding VLSI implementations. We emphasize how to efficiently handle four DAB transmission modes, time/frequency de-interleaving and path metric/survivor memory management in our development. Results show that our implementation has the characteristics of modular design, consuming less silicon area, and facilitating the extension for high transmission rate requirement. The core size of the resulting chip implementation is 4990×4930 μm² based on the Taiwan Semiconductor Manufacturing Company (TSMC) 0.6 μm single-polysilicon-triple-metal CMOS process

Keywords

CMOS digital integrated circuits; VLSI; Viterbi decoding; audio coding; convolutional codes; digital audio broadcasting; storage management; telecommunication channels; 0.6 micron; DAB channel decoder design; DAB transmission modes; Eureka-147 DAB system; Si; TSMC; Taiwan Semiconductor Manufacturing Company; VLSI implementations; de-interleaver; high transmission rate; modular design; path metric/survivor memory management; punctured Viterbi decoder; punctured convolutional coding; silicon area; single-polysilicon-triple-metal CMOS process; time/frequency de-interleaving; CMOS process; Communication industry; Decoding; Design engineering; Frequency; Industrial electronics; Memory management; Power dissipation; Silicon; Viterbi algorithm;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.793540

Filename

793540