Title :
A wideband CMOS sigma-delta modulator with incremental data weighted averaging
Author :
Kuo, Tai-Haur ; Chen, Kuan-Dar ; Yeng, Horng-Ru
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fDate :
1/1/2002 12:00:00 AM
Abstract :
A low-complexity high-speed circuit is proposed for the implementation of an incremental data weighted averaging (IDWA) technique used for reducing digital-to-analog converter (DAC) noise due to component mismatches. IDWA can achieve very good performance even when it is used with a low oversampling ratio (OSR), which reduces demands on circuit speed and power consumption. Therefore, the IDWA is highly suitable for wideband, low-power and small-area sigma-delta modulator (SDM) implementation. Incorporating the IDWA technique, a fourth-order feedforward (FF) SDM with an OSR of 12 and a 4-bit internal quantizer is implemented with a 2.5-V 0.25-μm CMOS process. Measurement results show that the SDM operating from a 2.5-V supply voltage can achieve respective dynamic ranges (DRs) of 84/80 dB and spurious-free dynamic ranges (SFDRs) of 90/85 dB with signal bandwidths of 1.25/2 MHz at sampling frequencies of 30/48 MHz. The power dissipation is less than 105 mW and the active area is 2.6 mm2. Wider bandwidth, lower OSR, less power, and lower supply voltage are achieved compared with two recently published 3.3-V/3-V CMOS wideband SDMs with comparable SNDR performance
Keywords :
CMOS integrated circuits; feedforward; high-speed integrated circuits; integrated circuit design; integrated circuit measurement; integrated circuit noise; low-power electronics; sigma-delta modulation; signal sampling; 0.25 micron; 1.25 MHz; 105 mW; 2 MHz; 2.5 V; 3 V; 3.3 V; 30 MHz; 4 bit; 48 MHz; CMOS measurement; CMOS process; CMOS wideband SDMs; DAC noise reduction; IDWA; IDWA technique; SNDR performance; active area; analog-to-digital converters; bandwidth; circuit speed; digital-to-analog converter noise; dynamic ranges; fourth-order feedforward SDM; incremental data weighted averaging; incremental data weighted averaging technique implementation; internal quantizer; low-complexity high-speed circuit; oversampling ratio; power consumption; sampling frequencies; signal bandwidths; small-area sigma-delta modulator implementation; spurious-free dynamic ranges; supply voltage; wideband CMOS sigma-delta modulator; wideband low-power sigma-delta modulator implementation; Bandwidth; CMOS process; Circuit noise; Delta-sigma modulation; Digital-analog conversion; Dynamic range; Energy consumption; Noise reduction; Voltage; Wideband;
Journal_Title :
Solid-State Circuits, IEEE Journal of
