Low-power high-performance arithmetic circuits and architectures

Author

Fahim, Amr M. ; Elmasry, Mohamed I.

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

Volume

37

Issue

1

fYear

2002

fDate

1/1/2002 12:00:00 AM

Firstpage

90

Lastpage

94

Abstract

A new class of dynamic differential logic families, swing limited logic (SLL), is proposed for low-power high-performance applications. Two implementations of SLL, short-circuit current logic (SC²L) and clock-pulse controlled logic (CPCL), are designed. Low power is achieved by aggressively reducing logic swing. Using a 0.35-μm CMOS technology and a nominal supply voltage of 3.3 V, an SC ²L 8-bit carry ripple adder (CRA) is implemented. It offers an order of magnitude less energy-delay product than several other logic families. Furthermore, two multipliers are constructed to demonstrate how SLL can be used in large circuit applications

Keywords

CMOS logic circuits; adders; carry logic; circuit simulation; integrated circuit design; integrated circuit testing; logic design; logic simulation; logic testing; low-power electronics; multiplying circuits; 0.35 micron; 3.3 V; 8 bit; CMOS technology; CPCL; SC²L carry ripple adder; SLL; SLL large circuit applications; adder; clock-pulse controlled logic; digital circuits; dynamic differential logic; energy-delay product; logic design; logic swing; low-power high-performance arithmetic architectures; low-power high-performance arithmetic circuits; multiplier; multipliers; multiply-accumulator; short-circuit current logic; supply voltage; swing limited logic; Arithmetic; CMOS logic circuits; CMOS technology; Clocks; Digital circuits; Energy consumption; Inverters; Logic design; Page description languages; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.974550

Filename

974550