Title :
Fast compensative design approach for the approximate squaring function
Author :
Sheu, Ming-hwa ; Lin, Su-Hon
Author_Institution :
Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan
fDate :
1/1/2002 12:00:00 AM
Abstract :
In this paper, a systematic compensation approach is presented to efficiently design the approximate squaring function with a simple combinational logic circuit. Also, a set of recursive Boolean equations for general outputs is derived such that the logic circuit can be rapidly designed and reused for various bit-width inputs. In logic implementation, our design approach possesses less circuit cost and lower critical delay. Moreover, in error analysis, the maximum relative error (MRE) and average relative error (ARE) of squaring approximation are significantly improved by at least 26.95% and 61.59%, respectively, as compared with the existing approaches. Finally, a 7-bit approximate squaring function chip is accomplished to verify the circuit performance based on 0.6-μm CMOS technology. The chip layout occupies 127×135 μm2 and the total number of transistors is 186
Keywords :
CMOS logic circuits; combinational circuits; error analysis; integrated circuit design; integrated circuit testing; logic design; logic testing; 0.6 micron; 127 micron; 135 micron; 7 bit; CMOS technology; approximate squaring function; approximate squaring function chip; approximate squaring function design; average relative error; chip layout; circuit cost; circuit performance; combinational logic circuit; compensative design approach; critical delay; error analysis; general outputs; input bit-width; logic circuit design; logic implementation; maximum relative error; recursive Boolean equations; squaring approximation error; systematic compensation approach; transistors; Algorithm design and analysis; CMOS technology; Circuit optimization; Combinational circuits; Costs; Delay; Equations; Logic arrays; Logic circuits; Logic design;
Journal_Title :
Solid-State Circuits, IEEE Journal of
