DocumentCode :
1557455
Title :
First Demonstration of Quasi-Planar Segmented-Channel MOSFET Design for Improved Scalability
Author :
Ho, Byron ; Sun, Xinghua ; Xu, Ningsheng ; Sako, Tokuei ; Maekawa, Keiichi ; Tomoyasu, M. ; Akasaka, Y. ; Bonnin, O. ; Nguyen, B.-Y. ; Liu, Tsu-Jae King
Author_Institution :
Department of Electrical Engineering and Computer Sciences, University of California at Berkeley , Berkeley, CA, USA
Volume :
59
Issue :
8
fYear :
2012
Firstpage :
2273
Lastpage :
2276
Abstract :
Quasi-planar segmented-channel MOSFETs (SegFETs) with gate lengths down to 
45 nm are fabricated using a conventional process flow by starting with a corrugated-silicon substrate. In comparison with control devices (fabricated using the same process flow, but with a planar-silicon substrate), the SegFETs show reduced short-channel effect due to enhanced electrostatic integrity. Despite having a smaller physical channel width, the SegFET can achieve comparable drive current per unit layout area as the conventional planar MOSFET design.
Keywords :
Educational institutions; Electron devices; Logic gates; MOSFET circuits; Silicon; Substrates; Sun; CMOS; MOSFET; multigate FET; scalability;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2012.2201721
Filename :
6239583
Link To Document :
