• DocumentCode
    1557541
  • Title

    To optimize electrical properties of the ultrathin (1.6 nm) nitride/oxide gate stacks with bottom oxide materials and post-deposition treatment

  • Author

    Chen, Chein-Hao ; Fang, Yean-Kuen ; Yang, Chih-Wei ; Ting, Shyh-Fann ; Tsair, Yong-Shiuan ; Wang, Ming-Fang ; Hou, Tuo-Hong ; Mo-Chiun Yu ; Chen, Shih-Chang ; Jang, Simon M. ; Yu, Douglas C H ; Liang, Mong-Song

  • Author_Institution
    Inst. of Microelectron., Nat. Cheng Kung Univ., Tainan, Taiwan
  • Volume
    48
  • Issue
    12
  • fYear
    2001
  • fDate
    12/1/2001 12:00:00 AM
  • Firstpage
    2769
  • Lastpage
    2776
  • Abstract
    The electrical properties affected by the bottom oxide materials and the post-deposition treatment on the ultrathin (down to 1.6 nm) nitride/oxide (N/O) stacks, prepared by rapid thermal chemical vapor deposition (RTCVD) with two-step NH3/N2O post-deposition annealing, for deep submicrometer dual-gate MOSFETs have been studied extensively. N/O stack with NO-grown bottom oxide exhibits fewer flat-band voltage shifts and higher hole and electron mobility, but suffers from worse leakage current than that with conventional O2-grown bottom oxide. In post-deposition treatment, increasing NH3 nitridation temperature can effectively reduce the equivalent oxide thickness (EOT) and improve leakage current reduction rate, but can result in worse mobility. Furthermore, the subsequent N2O annealing eliminates the defects and offers a contrary effect on the N/O stack in comparison with the NH3 nitridation step
  • Keywords
    CMOS integrated circuits; MOSFET; annealing; chemical vapour deposition; dielectric thin films; electron mobility; hole mobility; leakage currents; nitridation; rapid thermal processing; semiconductor device testing; silicon compounds; 1.6 nm; N/O stack; N2O; N2O annealing; NH3; NH3 nitridation; NH3 nitridation temperature; NO-grown bottom oxide; O2 -grown bottom oxide; RTCVD; SiON-SiO2; bottom oxide materials; defect elimination; dual-gate CMOS; dual-gate MOSFETs; electrical properties optimization; electron mobility; equivalent oxide thickness; flat-band voltage shifts; hole mobility; leakage current; leakage current reduction rate; post-deposition treatment; rapid thermal chemical vapor deposition; two-step NH3/N2O post-deposition annealing; ultrathin nitride/oxide gate stacks; ultrathin nitride/oxide stacks; Annealing; Boron; CMOS technology; High K dielectric materials; High-K gate dielectrics; Leakage current; MOSFETs; Silicon compounds; Tunneling; Ultra large scale integration;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.974702
  • Filename
    974702