DocumentCode
1557650
Title
Misalignment tolerance in the 100-nm T-gate recessed-channel Si nMOSFET
Author
Tao, Meng ; Gao, Feng ; Chen, Changyuan
Author_Institution
Dept. of Electr. Eng., Louisiana Tech. Univ., Ruston, LA, USA
Volume
48
Issue
12
fYear
2001
fDate
12/1/2001 12:00:00 AM
Firstpage
2951
Lastpage
2953
Abstract
Misalignment tolerance can be achieved in the 100-nm T-gate recessed-channel Si nMOSFET. The T-shaped gate accommodates channel-to-gate misalignment. Source/drain (S/D) implantation must be performed before gate patterning to achieve misalignment tolerance. The pregate implantation dose required for misalignment tolerance is ~20% of the total S/D dose, so lightly-doped drain can be maintained in this device
Keywords
MOSFET; elemental semiconductors; ion implantation; silicon; tolerance analysis; 100 nm; Si; T-gate recessed-channel Si nMOSFET; lightly-doped drain; misalignment tolerance; source/drain implantation; Dielectric devices; Doping; Etching; Fabrication; Implants; Lithography; MOSFET circuits; Maintenance engineering; Semiconductor device modeling; Silicon;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.974735
Filename
974735
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