Sub-100-nm vertical MOSFET with threshold voltage adjustment

Author

Mori, Kiyoshi ; Duong, AnhKim ; Richardson, William F.

Author_Institution

Sony Semicond. Corp., San Antonio, TX, USA

Volume

49

Issue

1

fYear

2002

fDate

1/1/2002 12:00:00 AM

Firstpage

61

Lastpage

66

Abstract

Sub-100-nm vertical MOSFET has been developed for fabrication with low cost processing. This is the first vertical MOSFET design that combines 1) a vertical L_DD structure processed with implantation and diffusion steps, 2) high-pressure oxide growing at source/drain (S/D) regions to reduce the gate overlapped capacitances, and 3) threshold voltage adjustment with a doped APCVD film. The drive current per unit channel width and S/D punch-through voltage are higher than that of previously published vertical MOSFETs. Fabrication processes are well established, and equipment of the 1 μm CMOS generation can be used to fabricate sub-100-nm channel length MOSFETs with good electrical characteristics and high performance

Keywords

MOSFET; VLSI; doping profiles; isolation technology; nanotechnology; oxidation; sputter etching; CMOS generation; I-V output characteristics; SIMS doping profile; VLSI; anisotropic plasma etching; doped APCVD film; drive current per unit channel width; epitaxial channel; front-end process flow; gate overlapped capacitances; high-pressure oxide; hot carrier effects; low cost processing; oxidation; source/drain punch-through voltage; source/drain regions; threshold voltage adjustment; vertical MOSFET; CMOS process; Capacitance; Character generation; Costs; Doping; Electric variables; Fabrication; MOSFET circuits; Substrates; Threshold voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.974750

Filename

974750